Systems on a chip (SOC) have been implemented in a number of capacities over the last few decades. SOC solutions offer the advantage of scaling which cannot be matched by board-level component integration. While analog and digital circuits have long been integrated onto a same substrate to provide a form of SOC that provides mixed signal capabilities, SOC solutions for mobile computing platforms, such as smart phones and tablets, remain elusive because these devices typically include components which operate with one or more of high voltage, high power, and high frequency. As such, conventional mobile computing platforms typically utilize group III-V compound semiconductors, such a GaAs heterojunction bipolar transistors (HBTs), to generate sufficient power amplification at GHz carrier frequencies and laterally diffused silicon MOS (LDMOS) technology to manage voltage conversion and power distribution (battery voltage regulation including step-up and/or step-down voltage conversion, etc.). Conventional silicon field effect transistors implementing CMOS technology then entail a third device technology utilized for logic and control functions within a mobile computing platform.
The plurality of transistor technologies utilized in a mobile computing platform limits scalability of the device as a whole and is therefore a barrier to greater functionality, higher levels of integration, lower costs, smaller form factors, etc. While an SOC solution for the mobile computing space that would integrate at two or more of these three device technologies is therefore attractive, one barrier to an SOC solution is the lack of a transistor technology having both a low Specific On Resistance (Ron), and a sufficiently high breakdown voltage (BV) (i.e., largest drain-to-source voltage YDS, a transistor can sustain before the advent of breakdown via avalanche and/or band-to-band tunneling at the drain-to-gate region).
Trade-offs in high voltage planar FETs can generally be shown in FIG. 1A, plotting Ron vs. BV. Baliga's limit is shown for various materials that form the plane on which a planar FET is fabricated. As can be seen from FIG. 1A, choosing a high mobility material to improve Ron typically results in a reduced BV because most high carrier mobility materials, such as InAs, have a low intrinsic breakdown field. The intrinsic breakdown field is a function of the bandgap of the semiconductor, such that a high mobility material, like InAs (˜25,000 cm2/V−s) having an energy gap of only 0.36 eV, has an intrinsic breakdown field of only 0.04 MV/cm. A high bandgap semiconductor, such as GaN (Eg=3.18 eV), while having a high intrinsic breakdown field of 3.3 MV/cm, has a lower mobility of approximately 2000 cm2/V−s, or less. For a given bandgap, the breakdown voltage of a transistor is a function of the gate-to-drain separation, Lgd, as shown in the cross-sectional view of FIG. 1B illustrating a typical planar high voltage FET with a lightly doped drain-to-gate region Lgd (e.g., an LDMOS device).
Referring further to FIG. 1B, the Ron limit is the lowest ON-state resistance that a transistor can achieve at a given BV and the lower the Ron, the more advantageous the transistor because power dissipation is reduced, a larger drive current can be provided, and higher Fmax (i.e., unity power gain frequency, or maximum oscillation). Ron includes the source and drain contact resistances (Rcc), channel resistance (Rch), and the drain-to-gate drift resistance (Rdrift), as illustrated in FIG. 1B. While Rdrift dominates at large voltages, at lower voltages (e.g., <100V), Rcc and Rch become more comparable to Rdrift. Hence, a device that has a reduced Rch for a given channel length can get closer to Baliga's limit for a given material as long as desirable breakdown characteristics are maintained. Such a device would therefore be highly advantageous for many circuit applications, particularly a SOC solution which integrates the RF integrated circuit (RFIC) and/or power management integrated circuit (PMIC) with the logic and control functions within a mobile computing platform.